Datasheet

76
11011B–ATARM–21-Feb-12
SAM3N
ISB - Instruction Synchronization Barrier - page 142
IT - If-Then condition block - page 133
LDM Rn{!}, reglist Load Multiple registers, increment after - page 97
LDMDB,
LDMEA
Rn{!}, reglist
Load Multiple registers, decrement
before
- page 97
LDMFD,
LDMIA
Rn{!}, reglist Load Multiple registers, increment after - page 97
LDR Rt, [Rn, #offset] Load Register with word - page 92
LDRB,
LDRBT
Rt, [Rn, #offset] Load Register with byte - page 92
LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes - page 92
LDREX Rt, [Rn, #offset] Load Register Exclusive - page 92
LDREXB Rt, [Rn] Load Register Exclusive with byte - page 92
LDREXH Rt, [Rn] Load Register Exclusive with halfword - page 92
LDRH,
LDRHT
Rt, [Rn, #offset] Load Register with halfword - page 92
LDRSB,
LDRSBT
Rt, [Rn, #offset] Load Register with signed byte - page 92
LDRSH,
LDRSHT
Rt, [Rn, #offset] Load Register with signed halfword - page 92
LDRT Rt, [Rn, #offset] Load Register with word - page 92
LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C page 110
LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C page 110
MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result - page 120
MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result - page 120
MOV, MOVS Rd, Op2 Move N,Z,C page 114
MOVT Rd, #imm16 Move Top - page 116
MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C page 114
MRS Rd, spec_reg
Move from special register to general
register
- page 143
MSR spec_reg, Rm
Move from general register to special
register
N,Z,C,V page 144
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z page 120
MVN, MVNS Rd, Op2 Move NOT N,Z,C page 114
NOP - No Operation - page 145
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C page 108
ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C page 108
POP reglist Pop registers from stack - page 99
PUSH reglist Push registers onto stack - page 99
Table 10-13. Cortex-M3 instructions (Continued)
Mnemonic Operands Brief description Flags Page