Datasheet

iv
11011B–ATARM–21-Feb-12
SAM3N
18.2 Product Dependencies ..................................................................................275
18.3 Functional Description ...................................................................................275
18.4 Enhanced Embedded Flash Controller (EEFC) User Interface .....................286
19 Fast Flash Programming Interface (FFPI) .......................................... 291
19.1 Description .....................................................................................................291
19.2 Parallel Fast Flash Programming ..................................................................291
20 SAM3N Boot Program ......................................................................... 303
20.1 Description .....................................................................................................303
20.2 Hardware and Software Constraints ..............................................................303
20.3 Flow Diagram ................................................................................................303
20.4 Device Initialization ........................................................................................303
20.5 SAM-BA Monitor ............................................................................................304
21 Bus Matrix (MATRIX) ........................................................................... 307
21.1 Description .....................................................................................................307
21.2 Embedded Characteristics ............................................................................307
21.3 Memory Mapping ...........................................................................................308
21.4 Special Bus Granting Techniques .................................................................308
21.5 Arbitration ......................................................................................................309
21.6 System I/O Configuration ..............................................................................311
21.7 Write Protect Registers ..................................................................................311
21.8 Bus Matrix (MATRIX) User Interface .............................................................312
22 Peripheral DMA Controller (PDC) ....................................................... 319
22.1 Description .....................................................................................................319
22.2 Embedded Characteristics ............................................................................319
22.3 Block Diagram ...............................................................................................320
22.4 Functional Description ...................................................................................321
22.5 Peripheral DMA Controller (PDC) User Interface ..........................................324
23 Clock Generator ................................................................................... 333
23.1 Description .....................................................................................................333
23.2 Embedded Characteristics ............................................................................333
23.3 Block Diagram ...............................................................................................334
23.4 Slow Clock .....................................................................................................335
23.5 Main Clock .....................................................................................................336
23.6 Divider and PLL Block ...................................................................................340