Datasheet

75
11011B–ATARM–21-Feb-12
SAM3N
10.9 Instruction set summary
The processor implements a version of the Thumb instruction set. Table 10-13 lists the sup-
ported instructions.
In Table 10-13:
• angle brackets, <>, enclose alternative forms of the operand
• braces, {}, enclose optional operands
• the Operands column is not exhaustive
• Op2 is a flexible second operand that can be either a register or a constant
• most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Table 10-13. Cortex-M3 instructions
Mnemonic Operands Brief description Flags Page
ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V page 105
ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V page 105
ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V page 105
ADR Rd, label Load PC-relative address - page 88
AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C page 108
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N,Z,C page 110
B label Branch - page 130
BFC Rd, #lsb, #width Bit Field Clear - page 126
BFI Rd, Rn, #lsb, #width Bit Field Insert - page 126
BIC, BICS
{Rd,} Rn, Op2 Bit Clear N,Z,C page 108
BKPT #imm Breakpoint - page 138
BL label Branch with Link - page 130
BLX Rm Branch indirect with Link - page 130
BX Rm Branch indirect - page 130
CBNZ Rn, label Compare and Branch if Non Zero - page 132
CBZ Rn, label Compare and Branch if Zero - page 132
CLREX - Clear Exclusive - page 102
CLZ Rd, Rm Count leading zeros - page 112
CMN, CMNS Rn, Op2 Compare Negative N,Z,C,V page 113
CMP, CMPS Rn, Op2 Compare N,Z,C,V page 113
CPSID iflags
Change Processor State, Disable
Interrupts
- page 139
CPSIE iflags
Change Processor State, Enable
Interrupts
- page 139
DMB - Data Memory Barrier - page 140
DSB - Data Synchronization Barrier - page 141
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C page 108