Datasheet

747
11011B–ATARM–21-Feb-12
SAM3N
Revision History
Doc. Rev.
11011B Comments
Change
Request
Ref.
Overview:
All mentions of 100-ball LFBGA changed into 100-ball TFBGA
Numerous updates
Section 7. “Product Mapping”, Heading was ‘Memories’. Changed to ‘Product Mapping’
Several updates to clarify that only 1 USART has ISO7816 capability
Two typos corrected in chapter 12 and 32
Section 5. “Power Considerations”: Figure 5-5 “Fast Start-Up Sources”, Changed from Edge detection to Level
detection. Section 24.10 “Fast Startup”, Added ‘SM’ for Fast Startup detection
Section “Features”, extented range for Flash (now from 16Kbytes) and SRAM (now from 4Kbytes)
Section 1.1 “Configuration Summary”, table extended
Section 2. “SAM3N Block Diagram”: Figure 2-1 “SAM3N 100-pin version Block Diagram” and Figure 2-2
“SAM3N 64-pin version Block Diagram” and Figure 2-3 “SAM3N 48-pin version Block Diagram”, updated
FLASH and SRAM boxes
Figure 3-1 “Signal Description List”, added table note for ’Internal pull-up disabled’ under ’’Comments’ in ‘ICE
and JTAG’ secion
Whole doc.. Replaced ‘SAM3N4/2/1’ by ‘SAM3N4/2/1/0/00’
Section 7.2::
Figure 7.2 “Embedded Memories”, added SAM3N0 and SAM3N00 product information
Figure 7.2.3 “Embedded Flash”, added SAM3N0 and SAM3N00 Flash bank information
Section 7.2.3.5 “Lock Regions”, added lock bit information for SAM3N0 and SAM3N00
Section 4.1.4 “100-ball TFBGA Pinout”, whole pinout table updated
Updated package dimensions in ‘Features’
Section 35-2 “DC Characteristics”, Pull-down Resistor values updated
Section 35-7 “DC Flash Characteristics”, Max value for ‘25°C /VDDCORE = 1.95V’ updated
Section 35-37 “Static Performance Characteristics”, updated values for Integral and Differential Non-linearity
parameters
Section 35-3 “1.8V Voltage Regulator Characteristics”, updated values for ‘Dropout Voltage’
Section 23.2 “Embedded Characteristics”, changed sentence “Processor Clock (HCLK), must be switched off...”
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7634
7685
7857
7913
7922
8106
7201
7965
rfo
rfo
8189
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CHIPID:
Section 25. “Chip Identifier (CHIPID)”: Figure 25-1 “ATSAM3N Chip IDs Register”, table updated with new chip
names
8106
Debug and Test Features:
Section 11. “Debug and Test Features”:
Section 11.5.7 “IEEE
®
1149.1 JTAG Boundary Scan”, Updated.
Section 11.4 “Debug and Test Pin Description”: Figure 11-1 “Debug and Test Signal List”, added table note for
TDO/TRACESWO
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8106