Datasheet

729
11011B–ATARM–21-Feb-12
SAM3N
Figure 35-19. Two-wire Serial Bus Timing
35.8.6 Embedded Flash Characteristics
The maximum operating frequency is given in tables 35-44 and 35-45 below but is limited by the Embedded Flash access
time when the processor is fetching code out of it. The tables 35-44 and 35-45 below give the device maximum operating
frequency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required to
access the Embedded Flash Memory
Note: The embedded flash is fully tested during production test, the flash contents is not set to a known state prior
to shipment. Therefore, the flash contents should be erased prior to programming an application.
Table 35-44. Embedded Flash Wait State VDDCORE set at 1.65V
FWS Read Operations Maximum Operating Frequency (MHz)
0 1 cycle 21
1 2 cycles 32
2 3 cycles 48
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
TWCK
TWD
t
r
Table 35-45. Embedded Flash Wait State VDDCORE set at 1.80V
FWS Read Operations Maximum Operating Frequency (MHz)
0 1 cycle 24
1 2 cycles 42
2 3 cycles 62
Table 35-46. AC Flash Characteristics
Parameter Conditions Min Typ Max Units
Program Cycle Time
per page including auto-erase 4.6 ms
per page without auto-erase 2.3 ms
Full Chip Erase 10 11.5 ms
Data Retention Not Powered or Powered 10 Years
Endurance
Write/Erase cycles @ 25°C
Write/Erase cycles @ 85°C
10K
30K
cycles