Datasheet

726
11011B–ATARM–21-Feb-12
SAM3N
Figure 35-18. USART SPI Slave mode: (Mode 0 or 3)
SCK
MISO
MOSI
SPI
9
SPI
10
SPI
11
NSS
SPI
14
SPI
15
Table 35-42. USART SPI Timings
Symbol Parameter Conditions Min Max Units
Master Mode
SPI
0
t
CPSCK
Period
1.8v domain
3.3v domain
t
CPMCK
/6 ns
SPI
1
Input Data Setup Time
1.8v domain
3.3v domain
0.5 * t
CPMCK
+ 2.6
0.5 * t
CPMCK
+ 2.4
ns
SPI
2
Input Data Hold Time
1.8v domain
3.3v domain
1.5 * t
CPMCK
-0.3
1.5 * t
CPMCK
-0.3
ns
SPI
3
Chip Select Active to Serial Clock
1.8v domain
3.3v domain
1.5 * t
CPSCK
- 0.9
1.5 * t
CPSCK
- 0.6
ns
SPI
4
Output Data Setup Time
1.8v domain
3.3v domain
-6
-4.7
3.8
3.6
ns
SPI
5
Serial Clock to Chip Select Inactive
1.8v domain
3.3v domain
1 *t
CPSCK
- 6
1 *t
CPSCK
- 4.6
ns
Slave Mode
SPI
6
t
CPSCK
falling to MISO
1.8V domain
3.3V domain
5.7
5.3
22.6
19.8
ns
SPI
7
MOSI Setup time before t
CPSCK
rises
1.8V domain
3.3V domain
2 * t
CPMCK
+ 1.9
2 * t
CPMCK
+ 1.7
ns
SPI
8
MOSI Hold time after t
CPSCK
rises
1.8v domain
3.3v domain
0
0
ns
SPI
9
t
CPSCK
rising to MISO
1.8v domain
3.3v domain
5.9
5.6
22
19.4
ns