Datasheet

724
11011B–ATARM–21-Feb-12
SAM3N
35.8.3.2 SPI Timings
Notes: 1. 3.3V domain: V
VDDIO
from 3.0V to 3.6V, maximum external capacitor = 30 pF.
2. 1.8V domain: V
VDDIO
from 1.65V to 1.95V, maximum external capacitor = 30 pF.
Note that in SPI master mode the SAM3N does not sample the data (MISO) on the opposite edge where data clocks out
(MOSI) but the same edge is used as shown in Figure 35-12 and Figure 35-13.
Table 35-41. SPI Timings
Symbol Parameter Conditions Min Max Units
SPI
0
MISO Setup time before SPCK rises (master)
3.3V domain
(1)
14.2 ns
1.8V domain
(2)
17 ns
SPI
1
MISO Hold time after SPCK rises (master)
3.3V domain
(1)
0ns
1.8V domain
(2)
0ns
SPI
2
SPCK rising to MOSI Delay (master)
3.3V domain
(1)
-2.7 2.6 ns
1.8V domain
(2)
-3.6 3.4 ns
SPI
3
MISO Setup time before SPCK falls (master)
3.3V domain
(1)
14.4 ns
1.8V domain
(2)
17 ns
SPI
4
MISO Hold time after SPCK falls (master)
3.3V domain
(1)
0ns
1.8V domain
(2)
0ns
SPI
5
SPCK falling to MOSI Delay (master)
3.3V domain
(1)
-2.4 2.8 ns
1.8V domain
(2)
-3.4 3.6 ns
SPI
6
SPCK falling to MISO Delay (slave)
3.3V domain
(1)
4.4 15.4 ns
1.8V domain
(2)
4.6 18.5 ns
SPI
7
MOSI Setup time before SPCK rises (slave)
3.3V domain
(1)
0ns
1.8V domain
(2)
0ns
SPI
8
MOSI Hold time after SPCK rises (slave)
3.3V domain
(1)
1.8 ns
1.8V domain
(2)
1.6 ns
SPI
9
SPCK rising to MISO Delay (slave)
3.3V domain
(1)
4.9 15.4 ns
1.8V domain
(2)
5.2 18.3 ns
SPI
10
MOSI Setup time before SPCK falls (slave)
3.3V domain
(1)
0ns
1.8V domain
(2)
0
SPI
11
MOSI Hold time after SPCK falls (slave)
3.3V domain
(1)
1.9 ns
1.8V domain
(2)
2ns
SPI
12
NPCS setup to SPCK rising (slave)
3.3V domain
(1)
6.3 ns
1.8V domain
(2)
6.4 ns
SPI
13
NPCS hold after SPCK falling (slave)
3.3V domain
(1)
0ns
1.8V domain
(2)
0ns
SPI
14
NPCS setup to SPCK falling (slave)
3.3V domain
(1)
6.4 ns
1.8V domain
(2)
6.4 ns
SPI
15
NPCS hold after SPCK falling (slave)
3.3V domain
(1)
0ns
1.8V domain
(2)
0ns