Datasheet

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11011B–ATARM–21-Feb-12
SAM3N
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is
because the handler for the new fault cannot preempt the currently executing fault handler.
• An exception handler causes a fault for which the priority is the same as or lower than the
currently executing exception.
• A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. This means that if a corrupted stack causes a fault, the fault handler
executes even though the stack push for the handler failed. The fault handler operates but the
stack contents are corrupted.
Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
10.7.3 Fault status registers and fault address registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused
the fault, as shown in Table 10-12.
10.7.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the hard fault han-
dlers. When the processor is in lockup state it does not execute any instructions. The processor
remains in lockup state until:
• it is reset
10.8 Power management
The Cortex-M3 processor sleep modes reduce power consumption:
• Backup Mode
•Wait Mode
• Sleep Mode
Table 10-12. Fault status and fault address registers
Handler
Status register
name
Address register
name Register description
Hard fault HFSR -
“Hard Fault Status Register” on page
187
Memory
management fault
MMFSR MMFAR
“Memory Management Fault Status
Register” on page 182
“Memory Management Fault Address
Register” on page 188
Bus fault BFSR BFAR
“Bus Fault Status Register” on page 183
“Bus Fault Address Register” on page
189
Usage fault UFSR -
“Usage Fault Status Register” on page
185