Datasheet

707
11011B–ATARM–21-Feb-12
SAM3N
35.3.3.1 Active Power Consumption with VDDCORE @ 1.8V
Table 35-13. Master Clock (MCK) and Core Clock variation (SAM3N4/2/1 MRL A)
Core Clock
/MCK (MHz)
AMP1 (VDDOUT) Consumption Unit
Division Fibonacci
128-bit Flash access 64-bit Flash access 128-bit Flash access 64-bit Flash access
mA
62 30 25.3 31.4 28.55
48 24.45 20.6 26.2 23.15
32 15.6 14.3 20 17.7
24 11.4 10.5 15.6 15
12 6.45 5.7 9.2 8.5
8 4.9 4.2 7.1 6.4
4 4.3 2.9 4.5 2.9
2 2.2 1.5 2.4 1.7
1 1.1 0.84 1.2 0.9
Table 35-14. Master Clock (MCK) and Core Clock variation (SAM3N1 MRL B and SAM3N0/00 MRL B)
Core Clock
/MCK (MHz)
AMP1 (VDDOUT) Consumption Unit
Division Fibonacci
128-bit Flash access 64-bit Flash access 128-bit Flash access 64-bit Flash access
mA
62 18.5 17.7 21.28 23.4
48 14.43 13.76 16.68 18.1
32 9.87 9.32 11.26 12.26
24 8.91 8.44 9.84 10.64
12 3.34 3.07 3.74 4.17
8 2.25 2.07 2.52 2.81
4 1.07 0.98 1.19 1.32
2 0.59 0.55 0.65 0.72
1 0.35 0.33 0.38 0.41
0.5 0.23 0.22 0.24 0.26
0.25 0.17 0.16 0.18 0.18
0.125 0.14 0.13 0.14 0.15
0.032 0.013 0.012 0.014 0.015