Datasheet

706
11011B–ATARM–21-Feb-12
SAM3N
35.3.3 Active Mode Power Consumption
The Active Mode configuration and measurements are defined as follows:
•VDDIO
= VDDIN = 3.3V
• VDDCORE = 1.8V (Internal Voltage regulator used) and 1.62V (external supply)
•T
A = 25° C
• Recursive Fibonacci Algorithm or division operation running from Flash memory
• All Peripheral clocks are deactivated.
• Master Clock (MCK) running at various frequencies with PLL or the fast RC oscillator
• Current measurement on AMP1 (VDDCORE)
Note: 1. Recursive Fibonacci is a high computation test whereas division operation is a low computa-
tion test.
Figure 35-8. Active Mode Measurement Setup
Table 35-12. Typical Current Consumption in Wait Mode
Conditions
VDDOUT
Consumption
(AMP1)
Total
Consumption
(AMP2) Unit
See Figure 35-7 on page 705 @25°C
There is no activity on the I/Os of the
device.
5.7 14.9 µA
VDDIO
VDDOUT
VDDCORE
VDDIN
Voltage
Regulator
VDDPLL
3.3V
AMP1