Datasheet

705
11011B–ATARM–21-Feb-12
SAM3N
35.3.2.2 Wait Mode
Figure 35-7. Measurement Setup for Wait Mode
• Core Clock and Master Clock Stopped
• Current measurement as shown in the above figure
• All Peripheral clocks deactivated
Table 35-12 gives current consumption in typical conditions.
Table 35-11. Sleep mode Current consumption versus Master Clock (MCK) variation
Core Clock/MCK (MHz)
VDDCORE Consumption
(AMP1)
Total Consumption
(AMP2)
Unit
62 8.16 10.7
mA
48 6.4 8.4
32 4.3 5.65
24 3.5 5.5
12 1.68 1.71
81.131.16
40.560.57
20.330.35
10.220.23
0.5 0.16 0.17
0.25 0.14 0.16
0.125 0.12 0.13
0.032 0.01 0.02
VDDIO
VDDOUT
VDDCORE
VDDIN
Voltage
Regulator
VDDPLL
3.3V
AMP1
AMP2