Datasheet

682
11011B–ATARM–21-Feb-12
SAM3N
34.6 Functional Description
34.6.1 Digital-to-analog Conversion
The DAC uses the master clock (MCK) to perform conversions.
Once a conversion has started, the DAC will take a setup time to provide the analog result on
the analog output.
Refer to the product electrical characteristics for more information.
34.6.2 Conversion Results
When a conversion is completed, the resulting analog value is available at the DAC channel
output.
34.6.3 Conversion Triggers
In internal trigger mode, conversion starts as soon as the DACC is enabled, data is written in the
DACC Conversion Data Register and an internal trigger event occurs (see Figure 34-2). The
internal trigger frequency is configurable through the CLKDIV field of the DACC Mode Register
and must not be above the maximum frequency allowed by the DAC.
In external trigger mode, the conversion waits for a rising edge event on the selected trigger to
begin (see Figure 34-3).
Warning: Disabling the external trigger mode will automatically set the DACC in internal trigger
mode.
Figure 34-2. Internal trigger
Figure 34-3. External trigger
CLKDIV/2
CLKDIV
CLKDIV CLKDIV
TXRDY
write
DACC_CDR
Internal
trigger
DACC
conversion
data1data2data3 data4
data1data2data3 data4
0123 4 3 210
Number of
bytes in FIFO
TXRDY
write
DACC_CDR
Extern
al
trigger
DACC
conversion
data1data2data3 data4
data1data2data3 data4
data5
data5
01 23 2 3 4 3 21 0
Number of
bytes in FIFO