Datasheet

658
11011B–ATARM–21-Feb-12
SAM3N
658
11011B–ATARM–21-Feb-12
SAM3N
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be
taken into consideration to program a precise value in the TRACKTIM field. See the product
ADC Characteristics section.
33.6.9 Buffer Structure
The PDC read channel is triggered each time new data is stored in ADC_LCDR register. The
same structure of data is repeatedly stored in ADC_LCDR register each time a trigger event
occurs. Depending on user mode of operation (ADC_MR, ADC_CHSR, ADC_SEQR1,
ADC_SEQR2) the structure differs. Each data transferred to PDC buffer, carried on a half-word
(16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register,
the 4 most significant bits are carrying the channel number thus allowing an easier post-process-
ing in the PDC buffer or better checking the PDC buffer integrity.
33.6.10 Write Protection Registers
To prevent any single software error that may corrupt ADC behavior, certain address spaces
can be write-protected by setting the WPEN bit in the “ADC Write Protect Mode Register”
(ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Pro-
tect Status Register (ADC_WPSR) is set and the field WPVSRC indicates in which register the
write access has been attempted.
The WPVS flag is reset by writing the ADC Write Protect Mode Register (ADC_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
“ADC Mode Register” on page 661
“ADC Channel Sequence 1 Register” on page 663
“ADC Channel Sequence 2 Register” on page 664
“ADC Channel Enable Register” on page 665
“ADC Channel Disable Register” on page 666
“ADC Extended Mode Register” on page 674
“ADC Compare Window Register” on page 675