Datasheet

648
11011B–ATARM–21-Feb-12
SAM3N
32.7.13 PWM Channel Update Register
Name: PWM_CUPD[0..3]
Addresses: 0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3]
Access: Write-only
CUPD: Channel Update Register
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modify-
ing the waveform period or duty-cycle.
Only the first 16 bits (internal channel counter size) are significant.
When CPD field of PWM_CMRx register = 0, the duty-cycle (CDTY of PWM_CDTYx register) is updated with the CUPD
value at the beginning of the next period.
When CPD field of PWM_CMRx register = 1, the period (CPRD of PWM_CPRDx register) is updated with the CUPD value
at the beginning of the next period.
31 30 29 28 27 26 25 24
CUPD
23 22 21 20 19 18 17 16
CUPD
15 14 13 12 11 10 9 8
CUPD
76543210
CUPD