Datasheet

631
11011B–ATARM–21-Feb-12
SAM3N
Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in
the Power Management Controller (PMC).
The PWM macrocell master clock, MCK, is divided in the clock generator module to provide dif-
ferent clocks available for all channels. Each channel can independently select one of the
divided clocks.
The clock generator is divided in three blocks:
– a modulo n counter which provides 11 clocks: F
MCK
, F
MCK
/2, F
MCK
/4, F
MCK
/8,
F
MCK
/16, F
MCK
/32, F
MCK
/64, F
MCK
/128, F
MCK
/256, F
MCK
/512, F
MCK
/1024
– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
clkB
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA
(DIVB) field value in the PWM Mode register (PWM_MR).
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register
are set to 0. This implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situa-
tion is also true when the PWM master clock is turned off through the Power Management
Controller.
32.6.2 PWM Channel
32.6.2.1 Block Diagram
Figure 32-3. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of three blocks:
• A clock selector which selects one of the clocks provided by the clock generator described in
Section 32.6.1 “PWM Clock Generator” on page 630.
• An internal counter clocked by the output of the clock selector. This internal counter is
incremented or decremented according to the channel configuration and comparators events.
The size of the internal counter is 16 bits.
• A comparator used to generate events according to the internal counter value. It also
computes the PWMx output waveform according to the configuration.
Comparator
PWMx
output waveform
Internal
Counter
Clock
Selector
inputs
from clock
generator
inputs from
APB bus
Channel