Datasheet

605
11011B–ATARM–21-Feb-12
SAM3N
605
11011B–ATARM–21-Feb-12
SAM3N
31.7.2 TC Block Mode Register
Name: TC_BMR
Addresses: 0x400100C4 (0), 0x400140C4 (1)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 612.
• TC0XC0S: External Clock Signal 0 Selection
• TC1XC1S: External Clock Signal 1 Selection
• TC2XC2S: External Clock Signal 2 Selection
• QDEN: Quadrature Decoder ENabled
0 = disabled.
1 = enables the quadrature decoder logic (filter, edge detection and quadrature decoding).
quadrature decoding (direction change) can be disabled using QDTRANS bit.
One of the POSEN or SPEEDEN bits must be also enabled.
31 30 29 28 27 26 25 24
–––––– MAXFILT
23 22 21 20 19 18 17 16
MAXFILT FILTER – IDXPHB SWAP
15 14 13 12 11 10 9 8
INVIDX INVB INVA EDGPHA QDTRANS SPEEDEN POSEN QDEN
76543210
– – TC2XC2S TC1XC1S TC0XC0S
Value Name Description
0 TCLK0 Signal connected to XC0: TCLK0
1– Reserved
2 TIOA1 Signal connected to XC0: TIOA1
3 TIOA2 Signal connected to XC0: TIOA2
Value Name Description
0 TCLK1 Signal connected to XC1: TCLK1
1– Reserved
2 TIOA0 Signal connected to XC1: TIOA0
3 TIOA2 Signal connected to XC1: TIOA2
Value Name Description
0 TCLK2 Signal connected to XC2: TCLK2
1– Reserved
2 TIOA1 Signal connected to XC2: TIOA1
3 TIOA2 Signal connected to XC2: TIOA2