Datasheet

603

11011B–ATARM–21-Feb-12

SAM3N

603

11011B–ATARM–21-Feb-12

SAM3N

31.7 Timer Counter (TC) User Interface

Notes: 1. Channel index ranges from 0 to 2.

2. Read-only if WAVE = 0

Table 31-4. Register Mapping

Offset

(1)

0x00 + channel * 0x40 + 0x00 Channel Control Register TC_CCR Write-only –

0x00 + channel * 0x40 + 0x04 Channel Mode Register TC_CMR Read-write 0

0x00 + channel * 0x40 + 0x08 Stepper Motor Mode Register TC_SMMR Read-write 0

0x00 + channel * 0x40 + 0x0C Reserved

0x00 + channel * 0x40 + 0x10 Counter Value TC_CV Read-only 0

0x00 + channel * 0x40 + 0x14 Register A TC_RA Read-write

(2)

0x00 + channel * 0x40 + 0x18 Register B TC_RB Read-write

(2)

0x00 + channel * 0x40 + 0x1C Register C TC_RC Read-write 0

0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-only 0

0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only –

0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only –

0x00 + channel * 0x40 + 0x2C Interrupt Mask Register TC_IMR Read-only 0

0xC0 Block Control Register TC_BCR Write-only –

0xC4 Block Mode Register TC_BMR Read-write 0

0xC8 QDEC Interrupt Enable Register TC_QIER Write-only –

0xCC QDEC Interrupt Disable Register TC_QIDR Write-only –

0xD0 QDEC Interrupt Mask Register TC_QIMR Read-only 0

0xD4 QDEC Interrupt Status Register TC_QISR Read-only 0

0xE4 Write Protect Mode Register TC_WPMR Read-write 0

0xFC Reserved – – –