Datasheet

602
11011B–ATARM–21-Feb-12
SAM3N
602
11011B–ATARM–21-Feb-12
SAM3N
Figure 31-20. 2-bit Gray Up/Down Counter.
31.6.16 Write Protection System
In order to bring security to the Timer Counter, a write protection system has been implemented.
The write protection mode prevent the write of TC_BMR, TC_CMRx, TC_SMMRx, TC_RAx,
TC_RBx, TC_RCx registers. When this mode is enabled and one of the protected registers
write, the register write request canceled.
Due to the nature of the write protection feature, enabling and disabling the write protection
mode requires the use of a security code. Thus when enabling or disabling the write protection
mode the WPKEY field of the TC_WPMR register must be filled with the “TIM” ASCII code (cor-
responding to 0x54494D) otherwise the register write will be canceled.
TIOAx
TIOBx
DOWNx
TC_RCx
WAVEx = GCENx =1