Datasheet

58
11011B–ATARM–21-Feb-12
SAM3N
10.5.4 Software ordering of memory accesses
The order of instructions in the program flow does not always guarantee the order of the corre-
sponding memory transactions. This is because:
• the processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
• the processor has multiple bus interfaces
• memory or devices in the memory map have different wait states
• some memory accesses are buffered or speculative.
“Memory system ordering of memory accesses” on page 56 describes the cases where the
memory system guarantees the order of memory accesses. Otherwise, if the order of memory
accesses is critical, software must include memory barrier instructions to force that ordering. The
processor provides the following memory barrier instructions:
10.5.4.1
DMB
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions com-
plete before subsequent memory transactions. See “DMB” on page 140.
10.5.4.2
DSB
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transac-
tions complete before subsequent instructions execute. See “DSB” on page 141.
10.5.4.3
ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory
transactions is recognizable by subsequent instructions. See “ISB” on page 142.
Use memory barrier instructions in, for example:
• Vector table. If the program changes an entry in the vector table, and then enables the
corresponding exception, use a DMB instruction between the operations. This ensures that if
the exception is taken immediately after being enabled the processor uses the new exception
vector.
• Self-modifying code. If a program contains self-modifying code, use an ISB instruction
immediately after the code modification in the program. This ensures subsequent instruction
execution uses the updated program.
0xA0000000 -
0xBFFFFFFF
External device Device
(1)
Shareable
(1)
-
0xC0000000 -
0xDFFFFFFF
Non-
shareable
(1)
0xE0000000 -
0xE00FFFFF
Private Peripheral
Bus
Strongly-
ordered
(1)
Shareable
(1)
-
0xE0100000 -
0xFFFFFFFF
Vendor-specific
device
(2)
Device
(1)
--
1. See “Memory regions, types and attributes” on page 55 for more information.
2. The Peripheral and Vendor-specific device regions have no additional access constraints.
Table 10-5. Memory region share ability policies (Continued)
Address range Memory region Memory type Shareability