Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TFBGA 100 (9x9) 32-Bit 48 MHz I/O number 79

11011B–ATARM–21-Feb-12

SAM3N

< Means that accesses are observed in program order, that is, A1 is always observed before A2.

10.5.3 Behavior of memory accesses

The behavior of accesses to each region in the memory map is:

The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends

that programs always use the Code region. This is because the processor has separate buses

that enable instruction fetches and data accesses to occur simultaneously.

10.5.3.1 Additional memory access constraints for shared memory

When a system includes shared memory, some memory regions have additional access con-

straints, and some regions are subdivided, as Table 10-5 shows:

Table 10-4. Memory access behavior

Address

range

Memory

region

Memory

type XN Description

0x00000000

0x1FFFFFFF

Code Normal

(1)

1. See “Memory regions, types and attributes” on page 55 for more information.

Executable region for program code. You can also put

data here.

0x20000000

0x3FFFFFFF

SRAM Normal

(1)

Executable region for data. You can also put code

here.

This region includes bit band and bit band alias areas,

see Table 10-6 on page 59.

0x40000000

0x5FFFFFFF

Peripheral Device

(1)

This region includes bit band and bit band alias areas,

see Table 10-6 on page 59.

0x60000000

0x9FFFFFFF

External

RAM

Normal

(1)

- Executable region for data.

0xA0000000

0xDFFFFFFF

External

device

Device

(1)

XN External Device memory

0xE0000000

0xE00FFFFF

Private

Peripheral

Bus

Strongly-

ordered

(1)

This region includes the NVIC, System timer, and

system control block.

0xE0100000

0xFFFFFFFF

Reserved Device

(1)

XN Reserved

Table 10-5. Memory region share ability policies

Address range Memory region Memory type Shareability