Datasheet

551
11011B–ATARM–21-Feb-12
SAM3N
551
11011B–ATARM–21-Feb-12
SAM3N
In SPI Master Mode:
• the external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set
to “1” in the Mode Register (US_MR), in order to generate correctly the serial clock on the
SCK pin.
• to obtain correct behavior of the receiver and the transmitter, the value programmed in CD
must be superior or equal to 6.
• if the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be
even to ensure a 50:50 mark/space ratio on the SCK pin, this value can be odd if the internal
clock is selected (MCK).
In SPI Slave Mode:
• the external clock (SCK) selection is forced regardless of the value of the USCLKS field in the
Mode Register (US_MR). Likewise, the value written in US_BRGR has no effect, because
the clock is provided directly by the signal on the USART SCK pin.
• to obtain correct behavior of the receiver and the transmitter, the external clock (SCK)
frequency must be at least 6 times lower than the system clock.