Datasheet

531
11011B–ATARM–21-Feb-12
SAM3N
531
11011B–ATARM–21-Feb-12
SAM3N
clock divider. This feature is only available when using USART normal mode. The fractional
Baud Rate is calculated using the following formula:
The modified architecture is presented below:
Figure 30-4. Fractional Baud Rate Generator
30.7.1.3 Baud Rate in Synchronous Mode or SPI Mode
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 3 times lower than the
system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the receive part
limits the SCK maximum frequency to MCK/3 in USART mode, or MCK/6 in SPI mode.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the
value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the
SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty
cycle on the SCK pin, even if the value programmed in CD is odd.
30.7.1.4 Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
Baudrate
SelectedClock
82 Over–()CD
FP
8
-------+
⎝⎠
⎛⎞
⎝⎠
⎛⎞
-----------------------------------------------------------------=
MCK/DIV
16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
3
0
1
0
1
FIDI
glitch-free
logic
Modulus
Control
FP
FP
BaudRate
SelectedClock
CD
--------------------------------------=
B
Di
Fi
------
f×=