Datasheet

52
11011B–ATARM–21-Feb-12
SAM3N
10.4.3.15 CONTROL register
The CONTROL register controls the stack used and the privilege level for software execution
when the processor is in Thread mode. See the register summary in Table 10-2 on page 44 for
its attributes. The bit assignments are:
• Active stack pointer
Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
• Thread mode privilege level
Defines the Thread mode privilege level:
0 = privileged
1 = unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CON-
TROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register.
In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and
exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, use the MSR instruc-
tion to set the Active stack pointer bit to 1, see “MSR” on page 144.
When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This
ensures that instructions after the ISB execute using the new stack pointer. See “ISB” on page 142
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
76543210
Reserved
Active Stack
Pointer
Thread Mode
Privilege
Level