Datasheet

506
11011B–ATARM–21-Feb-12
SAM3N
506
11011B–ATARM–21-Feb-12
SAM3N
29.3 Block Diagram
Figure 29-1. UART Functional Block Diagram
29.4 Product Dependencies
29.4.1 I/O Lines
The UART pins are multiplexed with PIO lines. The programmer must first configure the corre-
sponding PIO Controller to enable I/O line operations of the UART.
29.4.2 Power Management
The UART clock is controllable through the Power Management Controller. In this case, the pro-
grammer must first configure the PMC to enable the UART clock. Usually, the peripheral
identifier used for this purpose is 1.
Peripheral DMA Controller
Baud Rate
Generator
Transmit
Receive
Interrupt
Control
Peripheral
Bridge
Parallel
Input/
Output
UTXD
URXD
Power
Management
Controller
MCK
uart_irq
APB
UART
Table 29-1. UART Pin Description
Pin Name Description Type
URXD UART Receive Data Input
UTXD UART Transmit Data Output
Table 29-2. I/O Lines
Instance Signal I/O Line Peripheral
UART0 URXD0 PA9 A
UART0 UTXD0 PA10 A
UART1 URXD1 PB2 A
UART1 UTXD1 PB3 A