Datasheet

50
11011B–ATARM–21-Feb-12
SAM3N
10.4.3.12 Priority Mask Register
The PRIMASK register prevents activation of all exceptions with configurable priority. See the
register summary in Table 10-2 on page 44 for its attributes. The bit assignments are:
•PRIMASK
0 = no effect
1 = prevents the activation of all exceptions with configurable priority.
10.4.3.13 Fault Mask Register
The FAULTMASK register prevents activation of all exceptions. See the register summary in
Table 10-2 on page 44 for its attributes. The bit assignments are:
•FAULTMASK
0 = no effect
1 = prevents the activation of all exceptions.
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
76543210
Reserved PRIMASK
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
76543210
Reserved FAULTMASK