Datasheet

474
11011B–ATARM–21-Feb-12
SAM3N
474
11011B–ATARM–21-Feb-12
SAM3N
28.8.10 Read-write Flowcharts
The following flowcharts shown in Figure 28-16 on page 475, Figure 28-17 on page 476, Figure
28-18 on page 477, Figure 28-19 on page 478 and Figure 28-20 on page 479 give examples for
read and write operations. A polling or interrupt method can be used to check the status bits.
The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.
Figure 28-15. TWI Write Operation with Single Data Byte without Internal Address
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Transfer direction bit
Write ==> bit MREAD = 0
Load Transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1?
Read Status register
TXCOMP = 1?
Transfer finished
Ye s
Ye s
BEGIN
No
No
Write STOP Command
TWI_CR = STOP