Datasheet

473
11011B–ATARM–21-Feb-12
SAM3N
473
11011B–ATARM–21-Feb-12
SAM3N
28.8.7 Using the Peripheral DMA Controller (PDC)
The use of the PDC significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequences:
28.8.7.1 Data Transmit with the PDC
1. Initialize the transmit PDC (memory pointers, size, etc.).
2. Configure the master mode (DADR, CKDIV, etc.).
3. Start the transfer by setting the PDC TXTEN bit.
4. Wait for the PDC end TX flag.
5. Disable the PDC by setting the PDC TXDIS bit.
28.8.7.2 Data Receive with the PDC
1. Initialize the receive PDC (memory pointers, size - 1, etc.).
2. Configure the master mode (DADR, CKDIV, etc.).
3. Start the transfer by setting the PDC RXTEN bit.
4. Wait for the PDC end RX flag.
5. Disable the PDC by setting the PDC RXDIS bit.
28.8.8 Using the DMA Controller (DMAC)
The use of the DMAC significantlly reduces the CPU load.
To assure correct implementation, respect the following programming sequence.
1. Initialize the DMAC (channels, memory pointers , size, etc.);
1. Configure the master mode (DADR, CKDIV, etc.).
1. Enable the DMAC.
1. Wait for the DMAC flag.
1. Disable the DMAC.
28.8.9 SMBUS Quick Command (Master Mode Only)
The TWI interface can perform a Quick Command:
1. Configure the master mode (DADR, CKDIV, etc.).
2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to
be sent.
3. Start the transfer by setting the QUICK bit in the TWI_CR.
Figure 28-14. SMBUS Quick Command
TXCOMP
TXRDY
Write QUICK command in TWI_CR
TWD
AS DADR R/W P