Datasheet

464
11011B–ATARM–21-Feb-12
SAM3N
464
11011B–ATARM–21-Feb-12
SAM3N
28.2 Embedded Characteristics
•Two TWIs
• Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices
(Note:)
• One, Two or Three Bytes for Slave Address
• Sequential Read-write Operations
• Master, Multi-master and Slave Mode Operation
• Bit Rate: Up to 400 Kbits
• General Call Supported in Slave mode
• SMBUS Quick Command Supported in Master Mode
• Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data
Transfers in Master Mode Only
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
• Connection to DMA Controller (DMAC) Channel Capabilities Optimizes Data Transfers in
Master Mode Only
Note: See Table 28-1 for details on compatibility with I²C Standard.
28.3 List of Abbreviations
Table 28-2. Abbreviations
Abbreviation Description
TWI Two-wire Interface
A Acknowledge
NA Non Acknowledge
PStop
SStart
Sr Repeated Start
SADR Slave Address
ADR Any address except SADR
R Read
WWrite