Datasheet

459
11011B–ATARM–21-Feb-12
SAM3N
459
11011B–ATARM–21-Feb-12
SAM3N
• BITS: Bits Per Transfer
(See the
(Note:)
below the register table; Section 27.8.9 “SPI Chip Select Register” on page 458.)
The BITS field determines the number of data bits transferred. Reserved values should not be used.
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The
Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud
rate:
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
Note: If one of the SCBR fields inSPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they are
required to process transfers. If they are not used to transfer data, they can be set at any value.
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
Value Name Description
0 8_BIT 8_bits for transfer
1 9_BIT 9_bits for transfer
2 10_BIT 8_bits for transfer
3 11_BIT 8_bits for transfer
4 12_BIT 8_bits for transfer
5 13_BIT 8_bits for transfer
6 14_BIT 8_bits for transfer
7 15_BIT 8_bits for transfer
8 16_BIT 8_bits for transfer
10 – Reserved
11 – Reserved
12 – Reserved
13 – Reserved
14 – Reserved
15 – Reserved
16 – Reserved
SPCK Baudrate
MCK
SCBR
---------------=
Delay Before SPCK
DLYBS
MCK
-------------------=