Datasheet

458
11011B–ATARM–21-Feb-12
SAM3N
458
11011B–ATARM–21-Feb-12
SAM3N
27.8.9 SPI Chip Select Register
Name: SPI_CSRx[x=0..3]
Address: 0x40008030
Access: Read/Write
Note: SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the trans-
lated value unless the register is written.
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0 = The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first
transfer and if the two transfers occur on the same Chip Select.
1 = The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal dura-
tion of:
– (if DLYBCT field is different from 0)
– (if DLYBCT field equal 0)
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a different chip select.
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
76543210
BITS CSAAT CSNAAT NCPHA CPOL
DLYBCS
MCK
-----------------------
DLYBCS 1+
MCK
---------------------------------