Datasheet

44
11011B–ATARM–21-Feb-12
SAM3N
10.4.3.1 General-purpose registers
R0-R12 are 32-bit general-purpose registers for data operations.
10.4.3.2 Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indi-
cates the stack pointer to use:
•0 = Main Stack Pointer (MSP). This is the reset value.
•1 = Process Stack Pointer (PSP).
On reset, the processor loads the MSP with the value from address
0x00000000 .
10.4.3.3 Link Register
The Link Register (LR) is register R14. It stores the return information for subroutines, function
calls, and exceptions. On reset, the processor loads the LR value
0xFFFFFFFF .
Table 10-2. Core register set summary
Name
Type
(1)
1. Describes access type during program execution in thread mode and Handler mode. Debug
access can differ.
Required
privilege
(2)
2. An entry of Either means privileged and unprivileged software can access the register.
Reset
value Description
R0-R12 RW Either Unknown “General-purpose registers” on page 44
MSP RW Privileged
See
description
“Stack Pointer” on page 44
PSP RW Either Unknown “Stack Pointer” on page 44
LR RW Either 0xFFFFFFFF “Link Register” on page 44
PC RW Either
See
description
“Program Counter” on page 45
PSR RW Privileged
0x01000000 “Program Status Register” on page 46
ASPR RW Either 0x00000000
“Application Program Status Register” on
page 47
IPSR RO Privileged 0x00000000
“Interrupt Program Status Register” on page
48
EPSR RO Privileged 0x01000000
“Execution Program Status Register” on page
49
PRIMASK RW Privileged 0x00000000 “Priority Mask Register” on page 50
FAULTMASK RW Privileged 0x00000000 “Fault Mask Register” on page 50
BASEPRI RW Privileged 0x00000000 “Base Priority Mask Register” on page 51
CONTROL RW Privileged 0x00000000 “CONTROL register” on page 52