Datasheet

400
11011B–ATARM–21-Feb-12
SAM3N
400
11011B–ATARM–21-Feb-12
SAM3N
Notes: 1. Reset value of PIO_PSR depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
occurred.
Note: if an offset is not listed in the table it must be considered as reserved.
0x0104-
0x010C
Reserved – – –
0x0110 Reserved – – –
0x0114-
0x011C
Reserved – – –
Table 26-2. Register Mapping (Continued)
Offset Register Name Access Reset