Datasheet

364
11011B–ATARM–21-Feb-12
SAM3N
24.15.10 PMC Master Clock Register
Name: PMC_MCKR
Address: 0x400E0430
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374.
• CSS: Master Clock Source Selection
• PRES: Processor Clock Prescaler
• PLLDIV2: PLL Divisor by 2
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––PLLDIV2––––
76543210
–PRES––CSS
Value Name Description
0 SLOW_CLK Slow Clock is selected
1 MAIN_CLK Main Clock is selected
2 PLL_CLK PLL Clock is selected
3– Reserved
Value Name Description
0 CLK Selected clock
1 CLK_2 Selected clock divided by 2
2 CLK_4 Selected clock divided by 4
3 CLK_28 Selected clock divided by 8
4 CLK_16 Selected clock divided by 16
5 CLK_32 Selected clock divided by 32
6 CLK_64 Selected clock divided by 64
7 CLK_3 Selected clock divided by 3
PLLDIV2 PLL Clock Division
0 PLL clock frequency is divided by 1
1 PLL clock frequency is divided by 2