Datasheet

355
11011B–ATARM–21-Feb-12
SAM3N
24.15.1 PMC System Clock Enable Register
Name: PMC_SCER
Address: 0x400E0400
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374.
• PCKx: Programmable Clock x Output Enable
0 = No effect.
1 = Enables the corresponding Programmable Clock output.
24.15.2 PMC System Clock Disable Register
Name: PMC_SCDR
Address: 0x400E0404
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 374.
• PCKx: Programmable Clock x Output Disable
0 = No effect.
1 = Disables the corresponding Programmable Clock output.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCK2PCK1PCK0
76543210
––––––––
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCK2PCK1PCK0
76543210
––––––––