Datasheet

353
11011B–ATARM–21-Feb-12
SAM3N
24.14 Write Protection Registers
To prevent any single software error that may corrupt PMC behavior, certain address spaces
can be write protected by setting the WPEN bit in the “PMC Write Protect Mode Register”
(PMC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PMC Write
Protect Status Register (PMC_WPSR) is set and the field WPVSRC indicates in which register
the write access has been attempted.
The WPVS flag is reset by writing the PMC Write Protect Mode Register (PMC_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
“PMC System Clock Enable Register” on page 355
“PMC System Clock Disable Register” on page 355
“PMC Peripheral Clock Enable Register” on page 357
“PMC Peripheral Clock Disable Register” on page 358
“PMC Clock Generator Main Oscillator Register” on page 360
“PMC Clock Generator PLL Register” on page 363
“PMC Master Clock Register” on page 364
“PMC Programmable Clock Register” on page 365
“PMC Fast Startup Mode Register” on page 371
“PMC Fast Startup Polarity Register” on page 372
“PMC Oscillator Calibration Register” on page 376