Datasheet

350
11011B–ATARM–21-Feb-12
SAM3N
24.13 Clock Switching Details
24.13.1 Master Clock Switching Timings
Table 24-1 gives the worst case timings required for the Master Clock to switch from one
selected clock to another one. This is in the event that the prescaler is de-activated. When the
prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be
added.
24.13.2 Clock Switching Waveforms
Figure 24-4. Switch Master Clock from Slow Clock to PLL Clock
Table 24-1. Clock Switching Timings (Worst Case)
From Main Clock SLCK PLL Clock
To
Main Clock –
4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK
0.5 x Main Clock +
4.5 x SLCK
–
3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLL Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Slow Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
PLL Clock