Datasheet

35
11011B–ATARM–21-Feb-12
SAM3N
9.2 APB/AHB Bridge
The SAM3N4/2/1/0/00 product embeds one peripheral bridge:
The peripherals of the bridge are clocked by MCK.
9.3 Peripheral Signal Multiplexing on I/O Lines
The SAM3N product features 2 PIO controllers (48-pin and 64-pin version) or 3 PIO controllers
(100-pin version), PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set.
The SAM3N 64-pin and 100-pin PIO Controller controls up to 32 lines (see Table 9-2, “Multiplex-
ing on PIO Controller A (PIOA),” on page 36). Each line can be assigned to one of three
peripheral functions: A, B or C. The multiplexing tables in the following paragraphs define how
the I/O lines of the peripherals A, B and C are multiplexed on the PIO Controllers. The column
“Comments” has been inserted in this table for the user’s own comments; it may be used to track
how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within the tables.