Datasheet

343
11011B–ATARM–21-Feb-12
SAM3N
Figure 24-2. Master Clock Controller
24.5 Processor Clock Controller
The PMC features a Processor Clock Controller (HCLK) that implements the Processor Sleep
Mode. The Processor Clock can be disabled by executing the WFI (WaitForInterrupt) or the
WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Startup
Mode Register (PMC_FSMR).
The Processor Clock HCLK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Sleep Mode is achieved by disabling the Processor Clock,
which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the
product.
When Processor Sleep Mode is entered, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
24.6 SysTick Clock
The SysTick calibration value is fixed at 6000 which allows the generation of a time base of 1 ms
with SysTick clock at 6 MHz (max MCK/8).
24.7 Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by means
of the Peripheral Clock Controller. The user can individually enable and disable the Clock on the
peripherals.
The user can also enable and disable these clocks by writing Peripheral Clock Enable
(PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of the periph-
eral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are
automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral
has executed its last programmed operation before disabling the clock. This is to avoid data cor-
ruption or erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR and
PMC_PCSR) is the Peripheral Identifier defined at the product level. The bit number corre-
sponds to the interrupt source number assigned to the peripheral.
SLCK
Master Clock
Prescaler
MCK
PRESCSS
MAINCK
PLLCK
To the Processor
Clock Controller (PCK)
PMC_MCKR PMC_MCKR