Datasheet

342
11011B–ATARM–21-Feb-12
SAM3N
24.3 Block Diagram
Figure 24-1. General Clock Block Diagram
24.4 Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is
the clock provided to all the peripherals.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting
the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLL.
The Master Clock Controller is made up of a clock selector and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the
selected clock between 1 and 64, and the division by 3. The PRES field in PMC_MCKR pro-
grams the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a high-speed
clock to a lower one to inform the software when the change is actually done.
Power
Management
Controller
Main Clock
MAINCK
PLL Clock
PLLCK
ControlStatus
3-20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
MOSCSEL
Clock Generator
PLL and
Divider
XIN
XOUT
XIN32
XOUT32
Slow Clock
SLCK
EXTALSEL
(Supply Controller)
Embedded
32 kHz RC
Oscillator
32768 Hz
Crystal
Oscillator
0
1
0
1
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLCK
Prescaler
/1,/2,/3,/4,...,/64
HCLK
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
(PMC_MCKR)
Peripherals
Clock Controller
(PMC_PCERx)
ON/OFF
Prescaler
/1,/2,/4,...,/64
pck[..]
ON/OFF
FCLK
SysTick
Divider
/8
SLCK
MAINCK
PLLCK
Processor clock
Free runnning clock
Master clock
Embedded
4/8/12 MHz
Fast
RC Oscillator
Programmable Clock Controller
MCK
CSS
PRES
CSS
PRES