Datasheet

333
11011B–ATARM–21-Feb-12
SAM3N
23. Clock Generator
23.1 Description
The Clock Generator User Interface is embedded within the Power Management Controller and
is described in Section 24.15 ”Power Management Controller (PMC) User Interface”. However,
the Clock Generator registers are named CKGR_.
23.2 Embedded Characteristics
The Clock Generator is made up of:
• A Low Power 32,768 Hz Slow Clock Oscillator with bypass mode
• A Low Power RC Oscillator
• A 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator which can be bypassed
• A factory programmed Fast RC Oscillator, 3 output frequencies can be selected: 4, 8 or
12 MHz. By default 4 MHz is selected.
• A 60 to 130 MHz programmable PLL (input from 3.5 to 20 MHz), capable of providing the
clock MCK to the processor and to the peripherals.
It provides the following clocks:
• SLCK, the Slow Clock, which is the only permanent clock within the system
• MAINCK is the output of the Main Clock Oscillator selection: either the Crystal or Ceramic
Resonator-based Oscillator or 4/8/12 MHz Fast RC Oscillator
• PLLCK is the output of the Divider and 60 to 130 MHz programmable PLL