Datasheet

307
11011B–ATARM–21-Feb-12
SAM3N
21. Bus Matrix (MATRIX)
21.1 Description
The Bus Matrix implements a multi-layer AHB that enables parallel access paths between multi-
ple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix
interconnects 3 AHB Masters to
4 AHB Slaves. The normal latency to connect a master to a
slave is one cycle except for the default master of the accessed slave which is connected
directly (zero cycle latency).
The Bus Matrix user interface also provides a Chip Configuration User Interface with Registers
that allow to support application specific features.
21.2 Embedded Characteristics
21.2.1 Matrix Masters
The Bus Matrix of the SAM3N product manages 3
masters, which means that each master can
perform an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decodings.
21.2.2 Matrix Slaves
The Bus Matrix of the SAM3N product manages 4 slaves. Each slave has its own arbiter, allow-
ing a different arbitration per slave.
Table 21-1. List of Bus Matrix Masters
Master 0 Cortex-M3 Instruction/Data
Master 1 Cortex-M3 System
Master 2 Peripheral DMA Controller (PDC)
List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1 Internal ROM
Slave 2 Internal Flash
Slave 3 Peripheral Bridge