Datasheet

283
11011B–ATARM–21-Feb-12
SAM3N
The lock sequence is:
• The Set Lock command (SLB) and a page number to be protected are written in the Flash
Command Register.
• When the locking completes, the FRDY bit in the Flash Programming Status Register
(EEFC_FSR) rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR,
the interrupt line of the NVIC is activated.
• If the lock bit number is greater than the total number of lock bits, then the command has no
effect. The result of the SLB command can be checked running a GLB (Get Lock Bit)
command.
One error can be detected in the EEFC_FSR register after a programming sequence:
• a Command Error: a bad keyword has been written in the EEFC_FCR register.
It is possible to clear lock bits previously set. Then the locked region can be erased or pro-
grammed. The unlock sequence is:
• The Clear Lock command (CLB) and a page number to be unprotected are written in the
Flash Command Register.
• When the unlock completes, the FRDY bit in the Flash Programming Status Register
(EEFC_FSR) rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR,
the interrupt line of the NVIC is activated.
• If the lock bit number is greater than the total number of lock bits, then the command has no
effect.
One error can be detected in the EEFC_FSR register after a programming sequence:
• a Command Error: a bad keyword has been written in the EEFC_FCR register.
The status of lock bits can be returned by the Enhanced Embedded Flash Controller (EEFC).
The Get Lock Bit status sequence is:
• The Get Lock Bit command (GLB) is written in the Flash Command Register, FARG field is
meaningless.
• Lock bits can be read by the software application in the EEFC_FRR register. The first word
read corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as
it is meaningful. Extra reads to the EEFC_FRR register return 0.
For example, if the third bit of the first word read in the EEFC_FRR is set, then the third lock
region is locked.
One error can be detected in the EEFC_FSR register after a programming sequence:
• a Command Error: a bad keyword has been written in the EEFC_FCR register.
Note: Access to the Flash in read is permitted when a set, clear or get lock bit command is performed.
18.3.3.5 GPNVM Bit
GPNVM bits do not interfere with the embedded Flash memory plane. Refer to the product defi-
nition section for information on the GPNVM Bit Action.
The set GPNVM bit sequence is:
• Start the Set GPNVM Bit command (SGPB) by writing the Flash Command Register with the
SGPB command and the number of the GPNVM bit to be set.