Datasheet

262
11011B–ATARM–21-Feb-12
SAM3N
262
11011B–ATARM–21-Feb-12
SAM3N
16.4.6 Core Reset
The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described
previously in Section 16.4.5 ”Power Supply Reset”. The vddcore_nreset signal is normally
asserted before shutting down the core power supply and released as soon as the core power
supply is correctly regulated.
There are two additional sources which can be programmed to activate vddcore_nreset:
• a supply monitor detection
• a brownout detection
16.4.6.1 Supply Monitor Reset
The supply monitor is capable of generating a reset of the system. This can be enabled by set-
ting the SMRSTEN bit in the Supply Controller Supply Monitor Mode Register (SUPC_SMMR).
If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is imme-
diately activated for a minimum of 1 slow clock cycle.
16.4.6.2 Brownout Detector Reset
The brownout detector provides the bodcore_in signal to the SUPC which indicates that the volt-
age regulation is operating as programmed. If this signal is lost for longer than 1 slow clock
period while the voltage regulator is enabled, the Supply Controller can assert vddcore_nreset.
This feature is enabled by writing the bit, BODRSTEN (Brownout Detector Reset Enable) to 1 in
the Supply Controller Mode Register (SUPC_MR).
If BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low),
the vddcore_nreset signal is asserted for a minimum of 1 slow clock cycle and then released if
bodcore_in has been reactivated. The BODRSTS bit is set in the Supply Controller Status Reg-
ister (SUPC_SR) so that the user can know the source of the last reset.
Until bodcore_in is deactivated, the vddcore_nreset signal remains active.
16.4.7 Wake Up Sources
The wake up events allow the device to exit backup mode. When a wake up event is detected,
the Supply Controller performs a sequence which automatically reenables the core power
supply.