Datasheet

213
11011B–ATARM–21-Feb-12
SAM3N
Figure 12-4. User Reset State
12.4.4.4 Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These
commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1:
• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory
system, and, in particular, the Remap Command. The Peripheral Reset is generally used for
debug purposes.
Except for debug purposes , PERRST must always be used in conjunction with PROCRST
(PERRST and PROCRST set both at 1 simultaneously).
• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field
ERSTL in the Mode Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these com-
mands can be performed independently or simultaneously. The software reset lasts 3 Slow
Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is
detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn-
chronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field
ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field
RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in
RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Prog-
ress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left.
SLCK
periph_nreset
proc_nreset
NRST
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
MCK
Processor Startup
= 2 cycles
Any
Freq.
Resynch.
2 cycles
RSTTYP
Any XXX
Resynch.
2 cycles
0x4 = User Reset