Datasheet

206
11011B–ATARM–21-Feb-12
SAM3N
• Watchpoint event to halt core
The DWT contains counters for the items that follow:
• Clock cycle (CYCCNT)
• Folded instructions
• Load Store Unit (LSU) operations
• Sleep Cycles
• CPI (all instruction cycles except for the first cycle)
• Interrupt overhead
11.5.6 ITM (Instrumentation Trace Macrocell)
The ITM is an application driven trace source that supports printf style debugging to trace Oper-
ating System (OS) and application events, and emits diagnostic system information. The ITM
emits trace information as packets which can be generated by three different sources with sev-
eral priority levels:
• Software trace: Software can write directly to ITM stimulus registers. This can be done
thanks to the “printf” function. For more information, refer to Section 11.5.6.1 “How to
Configure the ITM”.
• Hardware trace: The ITM emits packets generated by the DWT.
• Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit
counter to generate the timestamp.
11.5.6.1 How to Configure the ITM
The following example describes how to output trace data in asynchronous trace mode.
• Configure the TPIU for asynchronous trace mode (refer to Section 11.5.6.3 “5.4.3. How to
Configure the TPIU”)
• Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the
Lock Access Register (Address: 0xE0000FB0)
• Write 0x00010015 into the Trace Control Register:
–Enable ITM
– Enable Synchronization packets
– Enable SWO behavior
– Fix the ATB ID to 1
• Write 0x1 into the Trace Enable Register:
– Enable the Stimulus port 0
• Write 0x1 into the Trace Privilege Register:
– Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will
result in the corresponding stimulus port being accessible in user mode.)
• Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit)
The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macro-
cell (ITM).
The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.