Datasheet

203
11011B–ATARM–21-Feb-12
SAM3N
Figure 11-3. Application Test Environment Example
11.4 Debug and Test Pin Description
Chip 2
Chip n
Chip 1 SAM3
SAM3-based Application Board In Test
JTAG
Connector
Te ster
Te st Adaptor
JTAG
Probe
Table 11-1. Debug and Test Signal List
Signal Name Function Type Active Level
Reset/Test
NRST Microcontroller Reset Input/Output Low
TST Test Select Input
SWD/JTAG
TCK/SWCLK Test Clock/Serial Wire Clock Input
TDI Test Data In Input
TDO/TRACESWO
Test Data Out/Trace Asynchronous
Data Out
Output
(1)
1.TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus the internal
pull-up corresponding to this PIO line must be enabled to avoid current consumption due to float-
ing input.
TMS/SWDIO
Test Mode Select/Serial Wire
Input/Output
Input
JTAGSEL JTAG Selection Input High