Datasheet

187
11011B–ATARM–21-Feb-12
SAM3N
10.21.12 Hard Fault Status Register
The HFSR gives information about events that activate the hard fault handler. See the register
summary in Table 10-30 on page 164 for its attributes.
This register is read, write to clear. This means that bits in the register read normally, but writing
1 to any bit clears that bit to 0. The bit assignments are:
• DEBUGEVT
Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.
•FORCED
Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either
because of priority or because it is disabled:
0 = no forced hard fault
1 = forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault.
• VECTTBL
Indicates a bus fault on a vector table read during exception processing:
0 = no bus fault on vector table read
1 = bus fault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the
exception.
The HFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is
cleared to 0 only by writing 1 to that bit, or by a reset.
31 30 29 28 27 26 25 24
DEBUGEVT FORCED Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
76543210
Reserved VECTTBL Reserved