Datasheet

179
11011B–ATARM–21-Feb-12
SAM3N
10.21.10 System Handler Control and State Register
The SHCSR enables the system handlers, and indicates:
• the pending status of the bus fault, memory management fault, and SVC exceptions
• the active status of the system handlers.
See the register summary in Table 10-30 on page 164 for the SHCSR attributes. The bit assign-
ments are:
• USGFAULTENA
Usage fault enable bit, set to 1 to enable
(1)
• BUSFAULTENA
Bus fault enable bit, set to 1 to enable
(3)
• MEMFAULTENA
Memory management fault enable bit, set to 1 to enable
(3)
• SVCALLPENDED
SVC call pending bit, reads as 1 if exception is pending
(2)
• BUSFAULTPENDED
Bus fault exception pending bit, reads as 1 if exception is pending
(2)
• MEMFAULTPENDED
Memory management fault exception pending bit, reads as 1 if exception is pending
(2)
• USGFAULTPENDED
Usage fault exception pending bit, reads as 1 if exception is pending
(2)
• SYSTICKACT
SysTick exception active bit, reads as 1 if exception is active
(3)
• PENDSVACT
PendSV exception active bit, reads as 1 if exception is active
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
USGFAULTENA BUSFAULTENA MEMFAULTENA
15 14 13 12 11 10 9 8
SVCALLPENDE
D
BUSFAULTPEND
ED
MEMFAULTPEN
DED
USGFAULTPEND
ED
SYSTICKACT PENDSVACT
Reserved
MONITORACT
76543210
SVCALLAVCT
Reserved
USGFAULTACT
Reserved
BUSFAULTACT MEMFAULTACT
1. Enable bits, set to 1 to enable the exception, or set to 0 to disable the exception.
2. Pending bits, read as 1 if the exception is pending, or as 0 if it is not pending. You can write to these bits to change the pending
status of the exceptions.
3. Active bits, read as 1 if the exception is active, or as 0 if it is not active. You can write to these bits to change the active status of
the exceptions, but see the Caution in this section.