Datasheet

176
11011B–ATARM–21-Feb-12
SAM3N
10.21.9 System Handler Priority Registers
The SHPR1-SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have
configurable priority.
SHPR1-SHPR3 are byte accessible. See the register summary in Table 10-30 on page 164 for
their attributes.
The system fault handlers and the priority field and register for each handler are:
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:4] of each field, and
bits[3:0] read as zero and ignore writes.
Table 10-32. System fault handler priority fields
Handler Field Register description
Memory management
fault
PRI_4
“System Handler Priority Register 1” on page 177
Bus fault PRI_5
Usage fault PRI_6
SVCall PRI_11 “System Handler Priority Register 2” on page 178
PendSV PRI_14
“System Handler Priority Register 3” on page 178
SysTick PRI_15