Datasheet

175
11011B–ATARM–21-Feb-12
SAM3N
1 = trap unaligned halfword and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.
• USERSETMPEND
Enables unprivileged software access to the STIR, see “Software Trigger Interrupt Register” on page 161:
0 = disable
1 = enable.
• NONEBASETHRDENA
Indicates how the processor enters Thread mode:
0 = processor can enter Thread mode only when no exception is active.
1 = processor can enter Thread mode from any level under the control of an EXC_RETURN value, see “Exception return”
on page 70.